Phase-aware Inverse Design for Silicon Photonic Logic Gates
Abstract
Inverse design has emerged as a powerful strategy for realizing compact photonic devices; however, its application to logic operations remains constrained by challenges in physical interpretability, architectural generality, and experimental validation. This work introduces an experimentally validated, unified, and physics-driven inverse design framework that implements all fundamental Boolean logic gates within a single silicon photonic architecture. Devices are fabricated within a 2 x 2 um^2 design region on a silicon-on-insulator platform, representing one of the smallest areas reported for photonic logic elements. By integrating amplitude, phase, and energy conservation into a composite figure of merit, the proposed approach enables direct control over constructive and destructive interference. Consequently, all logic functions, including XOR and three-input NAND/NOR operations, are achieved using a standardized configuration with two logical inputs and a bias port. Experimental results exhibit good agreement with numerical simulations across the C-band, confirming both the predictive accuracy and fabrication robustness of the method. Performance benchmarking reveals competitive contrast ratios compared to previous implementations, while providing a unified and scalable design strategy. These findings establish a physically interpretable and experimentally validated paradigm for inverse-designed photonic logic, advancing the development of compact, integrated optical computing systems.
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BibTeX
@misc{portes2026phaseaware,
title = {{Phase-aware Inverse Design for Silicon Photonic Logic Gates}},
author = {Ary Portes and Narges Dalvand and Felipe M. F. Teixeira and Omar P Vilela Neto and Julian L. Pita Ruiz and Michael Menard and Jhonattan C. Ramirez},
howpublished = {arXiv},
year = {2026},
month = sep,
doi = {10.48550/arxiv.2609.05734},
eprint = {2609.05734},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2609.05734},
note = {CC BY-NC-ND 4.0},
}
RIS
TY - UNPB
TI - Phase-aware Inverse Design for Silicon Photonic Logic Gates
AU - Ary Portes
AU - Narges Dalvand
AU - Felipe M. F. Teixeira
AU - Omar P Vilela Neto
AU - Julian L. Pita Ruiz
AU - Michael Menard
AU - Jhonattan C. Ramirez
PY - 2026
DA - 2026/09/04
PB - arXiv
DO - 10.48550/arxiv.2609.05734
UR - https://arxiv.org/abs/2609.05734
AB - Inverse design has emerged as a powerful strategy for realizing compact photonic devices; however, its application to logic operations remains constrained by challenges in physical interpretability, architectural generality, and experimental validation. This work introduces an experimentally validated, unified, and physics-driven inverse design framework that implements all fundamental Boolean logic gates within a single silicon photonic architecture. Devices are fabricated within a 2 x 2 um^2 design region on a silicon-on-insulator platform, representing one of the smallest areas reported for photonic logic elements. By integrating amplitude, phase, and energy conservation into a composite figure of merit, the proposed approach enables direct control over constructive and destructive interference. Consequently, all logic functions, including XOR and three-input NAND/NOR operations, are achieved using a standardized configuration with two logical inputs and a bias port. Experimental results exhibit good agreement with numerical simulations across the C-band, confirming both the predictive accuracy and fabrication robustness of the method. Performance benchmarking reveals competitive contrast ratios compared to previous implementations, while providing a unified and scalable design strategy. These findings establish a physically interpretable and experimentally validated paradigm for inverse-designed photonic logic, advancing the development of compact, integrated optical computing systems.
ER -