WISER: Systematic Design-Space Exploration of Trapped Ions with Multiplexed Control
Abstract
Trapped-ion Quantum Charge-Coupled Devices (QCCD) are a leading contender for quantum computing, but their scalability is constrained by control wiring and electronics. Wiring using Integrated Switching Electronics (WISE), a recently proposed QCCD architecture, reduces wiring through multiplexing and integrated switching hardware. However, this leaves an execution model with limited parallelism and limited flexibility in ion movement. Further, these devices need to be paired with a quantum error correction (QEC) code to enable fault-tolerant quantum computation (FTQC). Can WISE architectures efficiently support FTQC requirements? Which QEC choices, device and control parameters are practical? We present WISER, a cross-layer design-space exploration framework for trapped-ion systems with multiplexed control. WISER combines a WISE-specific SAT-based compiler, a physics-informed noise model and logical-memory simulation to estimate logical error rates, logical clock speeds and control power across hardware parameters and QEC families. Its compiler reduces routing time by $2.6−−18.8\times$ relative to a greedy WISE-compatible baseline. Our analysis provides concrete design guidance. Two-ion traps with $16$-way multiplexing, 8× lower than the original WISE proposal, give the fastest logical clock that meets our reliability and cold-stage power targets. With current hardware parameters, the distance-7 surface code is the only evaluated code to meet our early-FTQC screen, at 4.58Hz and 2.04W of DAC power per logical qubit. At this operating point, ion transport and recooling take $94−−96\%$ of the WISE cycle, and even without them sample-and-hold electrode charging leaves millisecond-scale syndrome-extraction rounds.
Related
- Residual-Guided Global-Drive Design in Trapped-Ion Quantum Simulators
- Simulation-guided design of an integrated photonic cavity for frequency-multiplexed Spontaneous Parametric Down Conversion
- Design and Finite-Element Analysis of a New Inclined Blade-Electrode Architecture for Trapped-Ion Quantum Information Processing
- All-optical universal control of nuclear-spin qudits in trapped neutral atoms
- Coherent optical control of a thousand qubits in a three-dimensional trapped-ion crystal
BibTeX
@misc{jones2026wiser,
title = {{WISER: Systematic Design-Space Exploration of Trapped Ions with Multiplexed Control}},
author = {Scott Jones and Song-qing-hao Yang and Prakash Murali},
howpublished = {arXiv},
year = {2026},
month = oct,
doi = {10.48550/arxiv.2609.13546},
eprint = {2609.13546},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2609.13546},
note = {CC BY-NC-ND 4.0},
}
RIS
TY - UNPB
TI - WISER: Systematic Design-Space Exploration of Trapped Ions with Multiplexed Control
AU - Scott Jones
AU - Song-qing-hao Yang
AU - Prakash Murali
PY - 2026
DA - 2026/10/02
PB - arXiv
DO - 10.48550/arxiv.2609.13546
UR - https://arxiv.org/abs/2609.13546
AB - Trapped-ion Quantum Charge-Coupled Devices (QCCD) are a leading contender for quantum computing, but their scalability is constrained by control wiring and electronics. Wiring using Integrated Switching Electronics (WISE), a recently proposed QCCD architecture, reduces wiring through multiplexing and integrated switching hardware. However, this leaves an execution model with limited parallelism and limited flexibility in ion movement. Further, these devices need to be paired with a quantum error correction (QEC) code to enable fault-tolerant quantum computation (FTQC). Can WISE architectures efficiently support FTQC requirements? Which QEC choices, device and control parameters are practical? We present WISER, a cross-layer design-space exploration framework for trapped-ion systems with multiplexed control. WISER combines a WISE-specific SAT-based compiler, a physics-informed noise model and logical-memory simulation to estimate logical error rates, logical clock speeds and control power across hardware parameters and QEC families. Its compiler reduces routing time by $2.6−−18.8\times$ relative to a greedy WISE-compatible baseline. Our analysis provides concrete design guidance. Two-ion traps with $16$-way multiplexing, 8× lower than the original WISE proposal, give the fastest logical clock that meets our reliability and cold-stage power targets. With current hardware parameters, the distance-7 surface code is the only evaluated code to meet our early-FTQC screen, at 4.58Hz and 2.04W of DAC power per logical qubit. At this operating point, ion transport and recooling take $94−−96\%$ of the WISE cycle, and even without them sample-and-hold electrode charging leaves millisecond-scale syndrome-extraction rounds.
ER -