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PreprintarXiv licencearXiv

Wafer-Level 1/f Noise Characterization of Scaled P-Type Nanosheets and Comparison with Planar HKMG Transistors

  • Ruben Asanovski
  • Anabela Veloso
  • Ben Kaczer
  • Naoto Horiguchi
  • Jacopo Franco
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Abstract

We present a comprehensive wafer-level 1/f noise study of scaled Gate-All-Around (GAA) p-type nanosheet transistors and benchmark them against large-area planar High- \k{appa} Metal Gate (HKMG) devices to assess the impact of device architecture on reliability. By statistically analyzing noise data from 188 nanosheets, we extract the effective trap density in the dielectric and compare it to that of planar transistors with identical gate stack, comparable processing thermal budgets, and no specific reliability anneals. The effective trap density extracted from 1/f noise is comparable in planar and nanosheet architectures. This indicates that transitioning to GAA nanosheets does not increase noise, which remains governed by gate stack quality.

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Cite

BibTeXRIS
BibTeX
@misc{asanovski2026waferlevel,
  title = {{Wafer-Level 1/f Noise Characterization of Scaled P-Type Nanosheets and Comparison with Planar HKMG Transistors}},
  author = {Ruben Asanovski and Anabela Veloso and Ben Kaczer and Naoto Horiguchi and Jacopo Franco},
  howpublished = {arXiv},
  year = {2026},
  month = sep,
  doi = {10.48550/arxiv.2609.08674},
  eprint = {2609.08674},
  archivePrefix = {arXiv},
  url = {https://arxiv.org/abs/2609.08674},
}
RIS
TY  - UNPB
TI  - Wafer-Level 1/f Noise Characterization of Scaled P-Type Nanosheets and Comparison with Planar HKMG Transistors
AU  - Ruben Asanovski
AU  - Anabela Veloso
AU  - Ben Kaczer
AU  - Naoto Horiguchi
AU  - Jacopo Franco
PY  - 2026
DA  - 2026/09/08
PB  - arXiv
DO  - 10.48550/arxiv.2609.08674
UR  - https://arxiv.org/abs/2609.08674
AB  - We present a comprehensive wafer-level 1/f noise study of scaled Gate-All-Around (GAA) p-type nanosheet transistors and benchmark them against large-area planar High- \k{appa} Metal Gate (HKMG) devices to assess the impact of device architecture on reliability. By statistically analyzing noise data from 188 nanosheets, we extract the effective trap density in the dielectric and compare it to that of planar transistors with identical gate stack, comparable processing thermal budgets, and no specific reliability anneals. The effective trap density extracted from 1/f noise is comparable in planar and nanosheet architectures. This indicates that transitioning to GAA nanosheets does not increase noise, which remains governed by gate stack quality.
ER  -