Low-cost approximate multipliers for quantum-dot cellular automata
- 1Department of Computer Engineering, Faculty of Engineering, Bu-Ali Sina University
Abstract
Quantum-dot cellular automata (QCA) is a promising beyond-complementary metal–oxide–semiconductor (CMOS) nanotechnology for ultra-low-energy digital systems, but the design of multipliers with low layout cost and power dissipation remains challenging. In parallel, approximate arithmetic has emerged as an effective strategy to trade bounded accuracy for significant reductions in area, delay, and energy in error-resilient applications. This paper introduces a family of approximate multipliers tailored to QCA and majority logic. At the Boolean level, we define an approximate 2 × 2 multiplier whose truth table deviates in only one out of sixteen input patterns (6.25% error rate), and an approximate 4:2 compressor that departs from the exact function in five out of 32 patterns (15.6% error rate), with errors confined to low-weight combinations. Two QCA realizations of the 2 × 2 tile are then proposed: a compact coplanar single-layer layout and a three-layer multilayer layout optimized for short interconnects and regular clock zoning. In addition, a majority-friendly approximate 4:2 compressor is implemented in QCA and employed to construct a 4 × 4 approximate multiplier by tiling the 2 × 2 blocks. All designs are evaluated in QCADesigner-E with a unified setup, reporting cell count, area, latency, cost, efficient complexity, and energy dissipation. Compared to the smallest previously reported 2 × 2 QCA multiplier, our most compact 2 × 2 realization reduces cell count, area, and cost by about 69%, 86.7%, and 86.7%, respectively, while maintaining low energy per operation. The proposed 4:2 compressor further cuts cell count and area by roughly 83% and 86.7%, and cost and efficient complexity by 98.8% and 98.1%, relative to the most compact delay-reporting QCA compressor. At the array level, the resulting 4 × 4 multiplier achieves up to 94–99% lower cost and 90–99% lower efficient complexity than representative QCA multipliers, while reducing average and total energy dissipation by more than 60% and 79% against recent multilayer and coplanar designs.
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BibTeX
@article{fayazi2026lowcost,
title = {{Low-cost approximate multipliers for quantum-dot cellular automata}},
author = {Shobeir Fayazi and Hatam Abdoli},
journal = {Scientific Reports},
year = {2026},
month = jul,
doi = {10.1038/s41598-026-62704-y},
url = {https://doi.org/10.1038/s41598-026-62704-y},
note = {CC BY},
}
RIS
TY - JOUR
TI - Low-cost approximate multipliers for quantum-dot cellular automata
AU - Shobeir Fayazi
AU - Hatam Abdoli
PY - 2026
DA - 2026/07/01
JO - Scientific Reports
DO - 10.1038/s41598-026-62704-y
UR - https://doi.org/10.1038/s41598-026-62704-y
AB - Quantum-dot cellular automata (QCA) is a promising beyond-complementary metal–oxide–semiconductor (CMOS) nanotechnology for ultra-low-energy digital systems, but the design of multipliers with low layout cost and power dissipation remains challenging. In parallel, approximate arithmetic has emerged as an effective strategy to trade bounded accuracy for significant reductions in area, delay, and energy in error-resilient applications. This paper introduces a family of approximate multipliers tailored to QCA and majority logic. At the Boolean level, we define an approximate 2 × 2 multiplier whose truth table deviates in only one out of sixteen input patterns (6.25% error rate), and an approximate 4:2 compressor that departs from the exact function in five out of 32 patterns (15.6% error rate), with errors confined to low-weight combinations. Two QCA realizations of the 2 × 2 tile are then proposed: a compact coplanar single-layer layout and a three-layer multilayer layout optimized for short interconnects and regular clock zoning. In addition, a majority-friendly approximate 4:2 compressor is implemented in QCA and employed to construct a 4 × 4 approximate multiplier by tiling the 2 × 2 blocks. All designs are evaluated in QCADesigner-E with a unified setup, reporting cell count, area, latency, cost, efficient complexity, and energy dissipation. Compared to the smallest previously reported 2 × 2 QCA multiplier, our most compact 2 × 2 realization reduces cell count, area, and cost by about 69%, 86.7%, and 86.7%, respectively, while maintaining low energy per operation. The proposed 4:2 compressor further cuts cell count and area by roughly 83% and 86.7%, and cost and efficient complexity by 98.8% and 98.1%, relative to the most compact delay-reporting QCA compressor. At the array level, the resulting 4 × 4 multiplier achieves up to 94–99% lower cost and 90–99% lower efficient complexity than representative QCA multipliers, while reducing average and total energy dissipation by more than 60% and 79% against recent multilayer and coplanar designs.
SN - 2045-2322
ER -