Energy-efficient CNN acceleration using approximate multipliers with error-aware weight precomputation
- 1Faculty of Electrical Engineering, Shahid Beheshti University
Abstract
Efficient inference of convolutional neural networks (CNNs) on energy-constrained devices has become increasingly important. Considering the extensive use of multiply-accumulate (MAC) operations in CNNs, efficient approximate multipliers have emerged as a promising solution. However, two major challenges remain: first, identifying a more suitable multiplier type for a given CNN model, and second, designing a reconfigurable multiplier architecture that supports a range of accuracy levels. This paper first investigates the key error metrics affecting classification accuracy in CNNs. Subsequently, three CNN-oriented 8-bit signed approximate multipliers are proposed, which rely on shift-based operations and a co-designed weight-precomputation scheme. Within this hardware-algorithm co-design, the precomputed weights are specifically optimized for the proposed multiplier architectures, thereby reducing effective CNN inference errors while simplifying the underlying hardware. These signed multipliers are appropriate for CNN inference applications. Furthermore, the proposed architecture is scalable and can be extended to support any n-bit multiplication. The proposed 8-bit structures are also applicable to operands of different bit widths, thereby offering flexibility that benefits CNN deployments. The proposed multipliers are evaluated across hardware and accuracy metrics during the inference phase of CNN models, including VGG10, VGG16, AlexNet, and ResNet-18. The proposed approximate multipliers were evaluated in both FPGA and ASIC implementations. The results demonstrate that the proposed multipliers achieve significant efficiency gains in both hardware implementation and accuracy.
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BibTeX
@article{sayadi2026energyefficient,
title = {{Energy-efficient CNN acceleration using approximate multipliers with error-aware weight precomputation}},
author = {Ladan Sayadi and Mohammad Hossein Moaiyeri and Somayeh Timarchi},
journal = {Scientific Reports},
year = {2026},
month = jul,
doi = {10.1038/s41598-026-63342-0},
url = {https://doi.org/10.1038/s41598-026-63342-0},
note = {CC BY},
}
RIS
TY - JOUR
TI - Energy-efficient CNN acceleration using approximate multipliers with error-aware weight precomputation
AU - Ladan Sayadi
AU - Mohammad Hossein Moaiyeri
AU - Somayeh Timarchi
PY - 2026
DA - 2026/07/01
JO - Scientific Reports
DO - 10.1038/s41598-026-63342-0
UR - https://doi.org/10.1038/s41598-026-63342-0
AB - Efficient inference of convolutional neural networks (CNNs) on energy-constrained devices has become increasingly important. Considering the extensive use of multiply-accumulate (MAC) operations in CNNs, efficient approximate multipliers have emerged as a promising solution. However, two major challenges remain: first, identifying a more suitable multiplier type for a given CNN model, and second, designing a reconfigurable multiplier architecture that supports a range of accuracy levels. This paper first investigates the key error metrics affecting classification accuracy in CNNs. Subsequently, three CNN-oriented 8-bit signed approximate multipliers are proposed, which rely on shift-based operations and a co-designed weight-precomputation scheme. Within this hardware-algorithm co-design, the precomputed weights are specifically optimized for the proposed multiplier architectures, thereby reducing effective CNN inference errors while simplifying the underlying hardware. These signed multipliers are appropriate for CNN inference applications. Furthermore, the proposed architecture is scalable and can be extended to support any n-bit multiplication. The proposed 8-bit structures are also applicable to operands of different bit widths, thereby offering flexibility that benefits CNN deployments. The proposed multipliers are evaluated across hardware and accuracy metrics during the inference phase of CNN models, including VGG10, VGG16, AlexNet, and ResNet-18. The proposed approximate multipliers were evaluated in both FPGA and ASIC implementations. The results demonstrate that the proposed multipliers achieve significant efficiency gains in both hardware implementation and accuracy.
SN - 2045-2322
ER -