Photonic sequential logic circuits for stateful intelligence

Abstract

By virtue of its high energy efficiency and ultra-low latency, optical computing is regarded as a highly promising computing paradigm in the post-Moore era. However, constructing a Turing-complete optical computing for next-generation AI paradigms, from large language models (LLMs) to real-time autonomous systems, requires not only stateless function mapping units, but also sequential logic circuits capable of storing historical states and processing dynamic data streams. Current photonic processors lack this temporal memory, and the state-of-the-art optical sequential schemes remain impractical due to signal attenuation and the absence of programmable clock control. Here, we propose a photonic sequential logic circuits (PSLC) to resolve this fundamental challenge. Leveraging a uniquely designed active optoelectronic feedback network, we construct a complete family of photonic sequential logic devices, comprehensively encompassing set-reset latches, D latches, and edge-triggered master-slave D flip-flops. We further construct photonic sequence detectors and asynchronous counters, verifying the capability of the architecture to execute both synchronous and asynchronous sequential tasks, alongside its system-level scalability. Ultimately, by combining the constructed PSLC with stateless function mapping units, we establish a universal hardware paradigm for stateful intelligence. We validate this paradigm by executing highly reliable real-time drone obstacle avoidance in the physical domain, alongside Shakespearean-style text generation in the symbolic domain. This work provides the crucial missing piece of the puzzle for optical computing to achieve stateful computing, establishing a definitive hardware foundation for advancing toward Turing-complete optical computing.

Phase-aware Inverse Design for Silicon Photonic Logic Gates
Ary Portes, Narges Dalvand, Felipe M. F. Teixeira +4
arXiv4 Sep 2026PreprintCC BY-NC-ND 4.0Full textOptics & photonicsarXiv
Operational theory for photonic circuits: generalizing linear optics beyond quantum theory
Ismaël Septembre, Matthias Kleinmann, Martin Plávala
arXiv29 Sep 2026PreprintarXiv licenceFull textOptics & photonics Quantum physics & quantum informationarXiv
Device-to-protocol simulation of spectrally-resolved quantum photonic circuits
Seongjin Jeon, Youngbin Kim, Joaquin Matres +2
arXiv12 Oct 2026PreprintarXiv licenceFull textQuantum physics & quantum informationarXiv
Low optical loss electrical isolation for multi-section monolithic GaSb-based photonic circuits
Md Ajwaad Zaman Quashef, Nouman Zia, Jukka Viheriälä +1
arXiv21 Oct 2026PreprintCC BY 4.0Full textOptics & photonicsarXiv
Ultra-low loss piezo-optomechanical low-confinement silicon nitride platform for visible wavelength quantum photonic circuits
Mayank Mishra, Gwangho Choi, Wenhua He +7
Nature Communications27 Oct 2026Peer-reviewedCC BY 4.0Full text1 citedOptics & photonicsCrossref

Cite

BibTeX RIS

BibTeX

@misc{li2026photonic,
  title = {{Photonic sequential logic circuits for stateful intelligence}},
  author = {Jingcheng Li and Wenkai Zhang and Jialong Zhang and Bo Wu and Qichao Ding and Hongli Wang and Hailong Zhou and Jianji Dong and Xinliang Zhang},
  howpublished = {arXiv},
  year = {2026},
  month = sep,
  doi = {10.48550/arxiv.2609.37235},
  eprint = {2609.37235},
  archivePrefix = {arXiv},
  url = {https://arxiv.org/abs/2609.37235},
}

RIS

TY  - UNPB
TI  - Photonic sequential logic circuits for stateful intelligence
AU  - Jingcheng Li
AU  - Wenkai Zhang
AU  - Jialong Zhang
AU  - Bo Wu
AU  - Qichao Ding
AU  - Hongli Wang
AU  - Hailong Zhou
AU  - Jianji Dong
AU  - Xinliang Zhang
PY  - 2026
DA  - 2026/09/29
PB  - arXiv
DO  - 10.48550/arxiv.2609.37235
UR  - https://arxiv.org/abs/2609.37235
AB  - By virtue of its high energy efficiency and ultra-low latency, optical computing is regarded as a highly promising computing paradigm in the post-Moore era. However, constructing a Turing-complete optical computing for next-generation AI paradigms, from large language models (LLMs) to real-time autonomous systems, requires not only stateless function mapping units, but also sequential logic circuits capable of storing historical states and processing dynamic data streams. Current photonic processors lack this temporal memory, and the state-of-the-art optical sequential schemes remain impractical due to signal attenuation and the absence of programmable clock control. Here, we propose a photonic sequential logic circuits (PSLC) to resolve this fundamental challenge. Leveraging a uniquely designed active optoelectronic feedback network, we construct a complete family of photonic sequential logic devices, comprehensively encompassing set-reset latches, D latches, and edge-triggered master-slave D flip-flops. We further construct photonic sequence detectors and asynchronous counters, verifying the capability of the architecture to execute both synchronous and asynchronous sequential tasks, alongside its system-level scalability. Ultimately, by combining the constructed PSLC with stateless function mapping units, we establish a universal hardware paradigm for stateful intelligence. We validate this paradigm by executing highly reliable real-time drone obstacle avoidance in the physical domain, alongside Shakespearean-style text generation in the symbolic domain. This work provides the crucial missing piece of the puzzle for optical computing to achieve stateful computing, establishing a definitive hardware foundation for advancing toward Turing-complete optical computing.
ER  -

Abstract

Related

Cite