Topological-Insulator Heterophase Gate Stacks for Transistor Electrostatics
Abstract
Conventional gate-stack scaling reduces dielectric thickness and increases permittivity while largely treating the position and electronic character of the gate-side screening boundary as fixed. Here we show that this boundary can be engineered by converting the surface of the topological insulator Bi\textsubscript{2}Se\textsubscript{3} into insulating high-κ BiF\textsubscript{3}. Position-resolved calculations reveal a gap-opened immediate amorphous-BiF\textsubscript{3}/crystalline-Bi\textsubscript{2}Se\textsubscript{3} interface and a reconstructed gap-closed Bi\textsubscript{2}Se\textsubscript{3}-derived state in the adjacent subinterface layer, accompanied by a localized interfacial dipole. Capacitor measurements independently resolve a finite series response consistent with electronic compressibility at this boundary; this response lowers the nominal stack capacitance. Despite this capacitance penalty, MoS\textsubscript{2} transistors with closely matched BiF\textsubscript{3} thicknesses and a common BiF\textsubscript{3}/MoS\textsubscript{2} channel-side material interface exhibit near-thermionic-limit switching, negligible hysteresis and substantially weaker subthreshold drain-bias dependence than BiF\textsubscript{3}-only controls. These results identify the position and electronic character of the gate-side screening boundary as additional design variables for transistor electrostatics beyond nominal dielectric capacitance.
Related
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BibTeX
@misc{song2026topologicalinsulator,
title = {{Topological-Insulator Heterophase Gate Stacks for Transistor Electrostatics}},
author = {Minuk Song and Jiwan Kim and MD Gius Uddin and Wonseok Kim and Jihun Park and Han Uk Lee and Dong Won Jeon and Dohyung Lee and Lide Yao and Jouko Lahtinen and Gyunghyun Jang and Soohyun Min and Yonas Tsegaye Megra and Xiaoqi Cui and Seungwoo Choi and Yunyun Dai and Sang Hoon Chae and Keun Su Kim and Dong-Ho Kang and Hyeon-Jin Shin and Wooseok Song and Seth Ariel Tongay and Chul-Ho Lee and Manish Chhowalla and Sung Beom Cho and Zhipei Sun and Kibog Park and Hoon Hahn Yoon},
howpublished = {arXiv},
year = {2026},
month = oct,
doi = {10.48550/arxiv.2609.30016},
eprint = {2609.30016},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2609.30016},
}
RIS
TY - UNPB
TI - Topological-Insulator Heterophase Gate Stacks for Transistor Electrostatics
AU - Minuk Song
AU - Jiwan Kim
AU - MD Gius Uddin
AU - Wonseok Kim
AU - Jihun Park
AU - Han Uk Lee
AU - Dong Won Jeon
AU - Dohyung Lee
AU - Lide Yao
AU - Jouko Lahtinen
AU - Gyunghyun Jang
AU - Soohyun Min
AU - Yonas Tsegaye Megra
AU - Xiaoqi Cui
AU - Seungwoo Choi
AU - Yunyun Dai
AU - Sang Hoon Chae
AU - Keun Su Kim
AU - Dong-Ho Kang
AU - Hyeon-Jin Shin
AU - Wooseok Song
AU - Seth Ariel Tongay
AU - Chul-Ho Lee
AU - Manish Chhowalla
AU - Sung Beom Cho
AU - Zhipei Sun
AU - Kibog Park
AU - Hoon Hahn Yoon
PY - 2026
DA - 2026/10/06
PB - arXiv
DO - 10.48550/arxiv.2609.30016
UR - https://arxiv.org/abs/2609.30016
AB - Conventional gate-stack scaling reduces dielectric thickness and increases permittivity while largely treating the position and electronic character of the gate-side screening boundary as fixed. Here we show that this boundary can be engineered by converting the surface of the topological insulator Bi\textsubscript{2}Se\textsubscript{3} into insulating high-κ BiF\textsubscript{3}. Position-resolved calculations reveal a gap-opened immediate amorphous-BiF\textsubscript{3}/crystalline-Bi\textsubscript{2}Se\textsubscript{3} interface and a reconstructed gap-closed Bi\textsubscript{2}Se\textsubscript{3}-derived state in the adjacent subinterface layer, accompanied by a localized interfacial dipole. Capacitor measurements independently resolve a finite series response consistent with electronic compressibility at this boundary; this response lowers the nominal stack capacitance. Despite this capacitance penalty, MoS\textsubscript{2} transistors with closely matched BiF\textsubscript{3} thicknesses and a common BiF\textsubscript{3}/MoS\textsubscript{2} channel-side material interface exhibit near-thermionic-limit switching, negligible hysteresis and substantially weaker subthreshold drain-bias dependence than BiF\textsubscript{3}-only controls. These results identify the position and electronic character of the gate-side screening boundary as additional design variables for transistor electrostatics beyond nominal dielectric capacitance.
ER -