Reconfigurable Bus-based Quantum Router for Modular Superconducting Processors
Abstract
Scaling superconducting quantum processors requires interconnects that provide both non-local connectivity and parallel entangling operations. While current quantum routers offer greater connectivity than nearest-neighbour topologies, their support for parallel, independently addressable two-qubit gates remains fundamentally limited, imposing severe compilation overheads that constitute a critical bottleneck. Here we introduce a bus-based reconfigurable quantum router that enables parallel controlled-Z (CZ) gates for modular superconducting processors. Constructed from a flux-tunable SQUID network, the router selectively connects interface qubits to two shared buses, allowing destructive interference to suppress idle interactions while supporting two disjoint CZ gates in parallel. Full-system Hamiltonian simulations yield parallel-gate infidelities ranging from 7.9×10−4 to 1.8×10−3 under the operating conditions considered, and an open-system analysis identifies the coherence requirements for high-fidelity operation. We further assess the circuit-level consequences using hardware-aware compilation and resource-constrained scheduling. For the 36-qubit quantum Fourier transform (QFT), QAOA-MaxCut, and random-pairing circuits, the router reduces the median SWAP count by up to 34% and the native CZ count by up to 20% relative to a matched two-dimensional grid. Circuit-depth reductions are workload-dependent, reaching 20% for QAOA-MaxCut but remaining negligible for the QFT despite its lower gate count. These results show that enhanced connectivity and schedulable parallelism provide complementary benefits for connectivity-intensive algorithms, establishing the router as a compiler-visible hardware resource and providing a scalable architectural pathway toward constructing highly connected modular superconducting quantum processors.
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BibTeX
@misc{yuan2026reconfigurable,
title = {{Reconfigurable Bus-based Quantum Router for Modular Superconducting Processors}},
author = {Benzheng Yuan and chaojie Zhang and Yangyang Fei and Chuanbing Han and Haoran He and Huihui Sun and Bo Zhao and Fudong Liu and Weilong Wang and Zheng Shan},
howpublished = {arXiv},
year = {2026},
month = sep,
doi = {10.48550/arxiv.2609.28881},
eprint = {2609.28881},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2609.28881},
}
RIS
TY - UNPB
TI - Reconfigurable Bus-based Quantum Router for Modular Superconducting Processors
AU - Benzheng Yuan
AU - chaojie Zhang
AU - Yangyang Fei
AU - Chuanbing Han
AU - Haoran He
AU - Huihui Sun
AU - Bo Zhao
AU - Fudong Liu
AU - Weilong Wang
AU - Zheng Shan
PY - 2026
DA - 2026/09/30
PB - arXiv
DO - 10.48550/arxiv.2609.28881
UR - https://arxiv.org/abs/2609.28881
AB - Scaling superconducting quantum processors requires interconnects that provide both non-local connectivity and parallel entangling operations. While current quantum routers offer greater connectivity than nearest-neighbour topologies, their support for parallel, independently addressable two-qubit gates remains fundamentally limited, imposing severe compilation overheads that constitute a critical bottleneck. Here we introduce a bus-based reconfigurable quantum router that enables parallel controlled-Z (CZ) gates for modular superconducting processors. Constructed from a flux-tunable SQUID network, the router selectively connects interface qubits to two shared buses, allowing destructive interference to suppress idle interactions while supporting two disjoint CZ gates in parallel. Full-system Hamiltonian simulations yield parallel-gate infidelities ranging from 7.9×10^−4 to 1.8×10^−3 under the operating conditions considered, and an open-system analysis identifies the coherence requirements for high-fidelity operation. We further assess the circuit-level consequences using hardware-aware compilation and resource-constrained scheduling. For the 36-qubit quantum Fourier transform (QFT), QAOA-MaxCut, and random-pairing circuits, the router reduces the median SWAP count by up to 34% and the native CZ count by up to 20% relative to a matched two-dimensional grid. Circuit-depth reductions are workload-dependent, reaching 20% for QAOA-MaxCut but remaining negligible for the QFT despite its lower gate count. These results show that enhanced connectivity and schedulable parallelism provide complementary benefits for connectivity-intensive algorithms, establishing the router as a compiler-visible hardware resource and providing a scalable architectural pathway toward constructing highly connected modular superconducting quantum processors.
ER -