Power Performance of CMOS-Compatible 100 nm Slanted-Gate GaN HEMTs in the Ka-Band
Abstract
This paper reports on the fabrication, physical characterization, and non-linear modeling of 100 nm slanted-gate GaN-on-silicon HEMTs processed using a CMOS-compatible platform. This technology enables state-of-the-art DC and RF performance, with a maximum drain current density of 0.9 A/mm, a peak transconductance of 605 mS/mm, and cut-off frequencies f T = 85 GHz and f max = 220 GHz at V DS = 10 V. Trapping effects investigated via conductance-versus-frequency (G-f) spectroscopy reveal two distinct interface trap populations (D it ~2-3 × 10 13 cm -2 /eV), whose temperature-dependent dynamics deviate from the Shockley-Read-Hall model and are attributed to multiphonon emission and quantum tunneling mechanisms, respectively. An enhanced Angelov-based compact model incorporating dedicated self-heating and current-collapse sub-circuits with capacitances derived directly from measured trap densities is validated through pulsed I-V and loadpull measurements, achieving excellent agreement at 40 GHz with a saturation output power of 24 dBm and a power-added efficiency (PAE) of 51%. These results establish a promising CMOS-compatible GaN-on-Si platform for Ka-band and millimeter-wave power amplifier applications.
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BibTeX
@article{fouzi2026power,
title = {{Power Performance of CMOS-Compatible 100 nm Slanted-Gate GaN HEMTs in the Ka-Band}},
author = {Yassine Fouzi and Martin Doublet and Benjamin Cart and Edouard Lebouvier and Etienne Okada and Erwan Morwan and Yveline Gobil and Fanny Morisot and Khatia Benotmane and Nicolas Defrance},
journal = {Electronics},
year = {2026},
month = oct,
doi = {10.3390/electronics15194544},
url = {https://hal.science/hal-05824829v1},
note = {CC BY 4.0},
}
RIS
TY - JOUR
TI - Power Performance of CMOS-Compatible 100 nm Slanted-Gate GaN HEMTs in the Ka-Band
AU - Yassine Fouzi
AU - Martin Doublet
AU - Benjamin Cart
AU - Edouard Lebouvier
AU - Etienne Okada
AU - Erwan Morwan
AU - Yveline Gobil
AU - Fanny Morisot
AU - Khatia Benotmane
AU - Nicolas Defrance
PY - 2026
DA - 2026/10/05
JO - Electronics
DO - 10.3390/electronics15194544
UR - https://hal.science/hal-05824829v1
AB - This paper reports on the fabrication, physical characterization, and non-linear modeling of 100 nm slanted-gate GaN-on-silicon HEMTs processed using a CMOS-compatible platform. This technology enables state-of-the-art DC and RF performance, with a maximum drain current density of 0.9 A/mm, a peak transconductance of 605 mS/mm, and cut-off frequencies f T = 85 GHz and f max = 220 GHz at V DS = 10 V. Trapping effects investigated via conductance-versus-frequency (G-f) spectroscopy reveal two distinct interface trap populations (D it ~2-3 × 10 13 cm -2 /eV), whose temperature-dependent dynamics deviate from the Shockley-Read-Hall model and are attributed to multiphonon emission and quantum tunneling mechanisms, respectively. An enhanced Angelov-based compact model incorporating dedicated self-heating and current-collapse sub-circuits with capacitances derived directly from measured trap densities is validated through pulsed I-V and loadpull measurements, achieving excellent agreement at 40 GHz with a saturation output power of 24 dBm and a power-added efficiency (PAE) of 51%. These results establish a promising CMOS-compatible GaN-on-Si platform for Ka-band and millimeter-wave power amplifier applications.
SN - 2079-9292
ER -