TD-Link: A Daisy-Chain Optical Architecture for Integrated Data Readout and Deterministic Timing Distribution in Large-Scale Detector Systems
Abstract
TD-Link is an optical communication architecture that combines high-throughput data readout and sub-nanosecond timing synchronization over a single fiber for large-scale detector systems. It adopts a multidrop daisy-chain ring topology connecting a Data Concentrator to up to sixteen FERS front-end boards per link, with up to eight links per concentrator. Operating at 3.125 Gb/s, TD-Link carries data, synchronization, and control traffic in the same serial stream through a token-based streaming protocol that minimizes per-hop latency and supports on-the-fly payload fragmentation. Deterministic latency is enforced at two levels. On the concentrator, transmitter lanes are aligned by using the half-full flag of the multi-gigabit transceiver (MGT) elastic buffer as a one-bit phase detector: a firmware state machine steps the transmit phase interpolator (PI) until the buffer pointer difference crosses half-depth, locking every lane to the same phase condition. On each front-end board, where the synchronization pulse must also cross from the recovered-clock to the transmit domain, the residual three-to-five-cycle ambiguity of the synchronizer is removed by a calibration-free multiphase oversampling time-to-digital converter (TDC) with 0.8 ns bins, which time-stamps the incoming edge on the transmit time base so that a scheduler regenerates it at a fixed, programmable latency. A Digital Dual Mixer Time Difference (DDMTD) circuit measures the inter-concentrator phase. Tests with CERN PicoTDC-equipped FERS boards show a board-to-board synchronization σ of 24 ps on the same ring, 27 ps across transceiver quads, and 28 ps across two cascaded concentrators, against an intrinsic front-end floor of 7 ps. Over more than one thousand cold boots without re-calibration, the boot-to-boot spread of the board-to-board skew stayed below 20 ps, consistent with the 18.6 ps phase-interpolator step.
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BibTeX
@misc{abba2026tdlink,
title = {{TD-Link: A Daisy-Chain Optical Architecture for Integrated Data Readout and Deterministic Timing Distribution in Large-Scale Detector Systems}},
author = {Andrea Abba and Gianluca Becuzzi and Matteo Bianchini and Francesco Caponio and Stefano Carsi and Alberto Cusimano and Camilla Maggio and Annalisa Mati and Daniele Ninci and Andrea Picchi and Carlo Tintori},
howpublished = {arXiv},
year = {2026},
month = oct,
doi = {10.48550/arxiv.2607.00904},
eprint = {2607.00904},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2607.00904},
}
RIS
TY - UNPB
TI - TD-Link: A Daisy-Chain Optical Architecture for Integrated Data Readout and Deterministic Timing Distribution in Large-Scale Detector Systems
AU - Andrea Abba
AU - Gianluca Becuzzi
AU - Matteo Bianchini
AU - Francesco Caponio
AU - Stefano Carsi
AU - Alberto Cusimano
AU - Camilla Maggio
AU - Annalisa Mati
AU - Daniele Ninci
AU - Andrea Picchi
AU - Carlo Tintori
PY - 2026
DA - 2026/10/12
PB - arXiv
DO - 10.48550/arxiv.2607.00904
UR - https://arxiv.org/abs/2607.00904
AB - TD-Link is an optical communication architecture that combines high-throughput data readout and sub-nanosecond timing synchronization over a single fiber for large-scale detector systems. It adopts a multidrop daisy-chain ring topology connecting a Data Concentrator to up to sixteen FERS front-end boards per link, with up to eight links per concentrator. Operating at 3.125 Gb/s, TD-Link carries data, synchronization, and control traffic in the same serial stream through a token-based streaming protocol that minimizes per-hop latency and supports on-the-fly payload fragmentation. Deterministic latency is enforced at two levels. On the concentrator, transmitter lanes are aligned by using the half-full flag of the multi-gigabit transceiver (MGT) elastic buffer as a one-bit phase detector: a firmware state machine steps the transmit phase interpolator (PI) until the buffer pointer difference crosses half-depth, locking every lane to the same phase condition. On each front-end board, where the synchronization pulse must also cross from the recovered-clock to the transmit domain, the residual three-to-five-cycle ambiguity of the synchronizer is removed by a calibration-free multiphase oversampling time-to-digital converter (TDC) with 0.8 ns bins, which time-stamps the incoming edge on the transmit time base so that a scheduler regenerates it at a fixed, programmable latency. A Digital Dual Mixer Time Difference (DDMTD) circuit measures the inter-concentrator phase. Tests with CERN PicoTDC-equipped FERS boards show a board-to-board synchronization σ of 24 ps on the same ring, 27 ps across transceiver quads, and 28 ps across two cascaded concentrators, against an intrinsic front-end floor of 7 ps. Over more than one thousand cold boots without re-calibration, the boot-to-boot spread of the board-to-board skew stayed below 20 ps, consistent with the 18.6 ps phase-interpolator step.
ER -