Design of Inductively Coupled Communication Link for Mooring Systems Based on Dual-Carrier Modulation
- 1School of Information and Communication Engineering, Hainan University, Haikou 570228, China
- 2Institute of Deep-Sea Science and Engineering, Chinese Academy of Sciences, Sanya 572000, China
- 3Sanya Oceanographic Institution, Ocean University of China, Sanya 572024, China
Abstract
To address the challenge in real-time communication mooring systems where clock synchronization and data transmission are difficult to achieve simultaneously over a single jacketed steel cable loop, this paper develops a dual-carrier inductively coupled communication (ICC) scheme based on the design concept of frequency division multiplexing (FDM). Two carrier signals with distinct frequencies and modulation schemes are loaded in parallel onto the same cable loop, using binary differential phase-shift keying (2DPSK) to carry minute-level data communication and binary phase-shift keying (2PSK) to carry microsecond-level clock synchronization broadcasts. To resolve inter-carrier crosstalk and channel attenuation, a single-stage multiple feedback (MFB) narrow bandpass filter and a three-stage analog front-end consisting of “passive high-impedance filtering, differential-to-single-ended conversion, and multistage active high-gain amplification” are designed in hardware, achieving efficient separation of hybrid signals and suppression of noise. In software, a combined demodulation architecture based on digital delay differential and zero-crossing decision, along with a digital Costas loop, is constructed to accomplish data demodulation and high-precision pulse-per-second (PPS) clock recovery. Laboratory and 300 m nearshore sea trial results demonstrate that the system achieves a packet reception ratio of over 89.60%, an error-free packet delivery ratio exceeding 83.24% with a bit error ratio below 0.22%, and maintains a clock synchronization error within 200 µs.
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BibTeX
@article{zhang2026design,
title = {{Design of Inductively Coupled Communication Link for Mooring Systems Based on Dual-Carrier Modulation}},
author = {Shengzong Zhang and Peng Luo and Zejin Sun and Junlin Pan and He Wu and Chuan Tian},
journal = {Journal of Marine Science and Engineering},
year = {2026},
month = oct,
doi = {10.3390/jmse14201898},
url = {https://doi.org/10.3390/jmse14201898},
note = {CC BY},
}
RIS
TY - JOUR
TI - Design of Inductively Coupled Communication Link for Mooring Systems Based on Dual-Carrier Modulation
AU - Shengzong Zhang
AU - Peng Luo
AU - Zejin Sun
AU - Junlin Pan
AU - He Wu
AU - Chuan Tian
PY - 2026
DA - 2026/10/26
JO - Journal of Marine Science and Engineering
DO - 10.3390/jmse14201898
UR - https://doi.org/10.3390/jmse14201898
AB - To address the challenge in real-time communication mooring systems where clock synchronization and data transmission are difficult to achieve simultaneously over a single jacketed steel cable loop, this paper develops a dual-carrier inductively coupled communication (ICC) scheme based on the design concept of frequency division multiplexing (FDM). Two carrier signals with distinct frequencies and modulation schemes are loaded in parallel onto the same cable loop, using binary differential phase-shift keying (2DPSK) to carry minute-level data communication and binary phase-shift keying (2PSK) to carry microsecond-level clock synchronization broadcasts. To resolve inter-carrier crosstalk and channel attenuation, a single-stage multiple feedback (MFB) narrow bandpass filter and a three-stage analog front-end consisting of “passive high-impedance filtering, differential-to-single-ended conversion, and multistage active high-gain amplification” are designed in hardware, achieving efficient separation of hybrid signals and suppression of noise. In software, a combined demodulation architecture based on digital delay differential and zero-crossing decision, along with a digital Costas loop, is constructed to accomplish data demodulation and high-precision pulse-per-second (PPS) clock recovery. Laboratory and 300 m nearshore sea trial results demonstrate that the system achieves a packet reception ratio of over 89.60%, an error-free packet delivery ratio exceeding 83.24% with a bit error ratio below 0.22%, and maintains a clock synchronization error within 200 µs.
SN - 2077-1312
ER -