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PreprintCC BY 4.0arXiv

12 nm FinFETs from 292 K to 10 mK: Characterization and a Temperature-Continuous Compact Model for Qubit Control

  • DaKyung Lee
  • Liyang Jin
  • Jungmin Lee
  • Rohit Rangaraj
  • Linbo Shao
  • Jeffrey S. Walling
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Abstract

We report cryogenic characterization and compact modeling of GlobalFoundries (GF) 12LP regular-voltage-threshold (RVT) n- and p-FinFETs, measured from 292 K to 10 mK. Both devices retain sub-Kelvin gate control without carrier freeze-out, with the n-type device exhibiting an intrinsic sub-threshold slope (SS) floor of 24.8 mV/dec. To bypass high on-chip series routing resistance that confounds peak-gm extraction, we adopt a fixed-current (3.26 uA/um) methodology. These low-current metrics inform a continuous 1.36 K to 292 K compact model using dynamic parameter injection, preserving room-temperature process development kit (PDK) qualification.

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Cite

BibTeXRIS
BibTeX
@misc{lee2026finfets,
  title = {{12 nm FinFETs from 292 K to 10 mK: Characterization and a Temperature-Continuous Compact Model for Qubit Control}},
  author = {DaKyung Lee and Liyang Jin and Jungmin Lee and Rohit Rangaraj and Linbo Shao and Jeffrey S. Walling},
  howpublished = {arXiv},
  year = {2026},
  month = sep,
  doi = {10.48550/arxiv.2609.11963},
  eprint = {2609.11963},
  archivePrefix = {arXiv},
  url = {https://arxiv.org/abs/2609.11963},
  note = {CC BY 4.0},
}
RIS
TY  - UNPB
TI  - 12 nm FinFETs from 292 K to 10 mK: Characterization and a Temperature-Continuous Compact Model for Qubit Control
AU  - DaKyung Lee
AU  - Liyang Jin
AU  - Jungmin Lee
AU  - Rohit Rangaraj
AU  - Linbo Shao
AU  - Jeffrey S. Walling
PY  - 2026
DA  - 2026/09/01
PB  - arXiv
DO  - 10.48550/arxiv.2609.11963
UR  - https://arxiv.org/abs/2609.11963
AB  - We report cryogenic characterization and compact modeling of GlobalFoundries (GF) 12LP regular-voltage-threshold (RVT) n- and p-FinFETs, measured from 292 K to 10 mK. Both devices retain sub-Kelvin gate control without carrier freeze-out, with the n-type device exhibiting an intrinsic sub-threshold slope (SS) floor of 24.8 mV/dec. To bypass high on-chip series routing resistance that confounds peak-gm extraction, we adopt a fixed-current (3.26 uA/um) methodology. These low-current metrics inform a continuous 1.36 K to 292 K compact model using dynamic parameter injection, preserving room-temperature process development kit (PDK) qualification.
ER  -