Demand-Driven Routing Space for Lattice-Surgery Compilation
Abstract
Lattice-surgery compilation places logical qubits on a grid of surface-code tiles and routes their interactions. Sparse static layouts limit routing contention but reserve space that often remains idle. Reducing this reservation requires balancing area savings against additional gate serialization and qubit movement. In this paper, we present a co-designed dynamic architecture and compiler that allocates routing space according to circuit demand. The architecture preserves a fixed virtual qubit floorplan while allowing its physical spacing to change between execution stages. The compiler coordinates placement, scheduling, and routing to implement lattice surgeries using fewer physical qubits. Across our application benchmarks, our method reduces space-time volume by 55.6% in geometric mean and compiles 75.5 times faster than the evaluated DasCot configuration. A circuit-synthesis case study shows how our compiler exposes optimization tradeoffs.
Related
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BibTeX
@misc{wang2026demanddriven,
title = {{Demand-Driven Routing Space for Lattice-Surgery Compilation}},
author = {Hanyu Wang and Wan-Hsuan Lin and Zihan Chen and Eddy Z. Zhang and Jason Cong},
howpublished = {arXiv},
year = {2026},
month = oct,
doi = {10.48550/arxiv.2610.30747},
eprint = {2610.30747},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2610.30747},
note = {CC BY 4.0},
}
RIS
TY - UNPB
TI - Demand-Driven Routing Space for Lattice-Surgery Compilation
AU - Hanyu Wang
AU - Wan-Hsuan Lin
AU - Zihan Chen
AU - Eddy Z. Zhang
AU - Jason Cong
PY - 2026
DA - 2026/10/22
PB - arXiv
DO - 10.48550/arxiv.2610.30747
UR - https://arxiv.org/abs/2610.30747
AB - Lattice-surgery compilation places logical qubits on a grid of surface-code tiles and routes their interactions. Sparse static layouts limit routing contention but reserve space that often remains idle. Reducing this reservation requires balancing area savings against additional gate serialization and qubit movement. In this paper, we present a co-designed dynamic architecture and compiler that allocates routing space according to circuit demand. The architecture preserves a fixed virtual qubit floorplan while allowing its physical spacing to change between execution stages. The compiler coordinates placement, scheduling, and routing to implement lattice surgeries using fewer physical qubits. Across our application benchmarks, our method reduces space-time volume by 55.6% in geometric mean and compiles 75.5 times faster than the evaluated DasCot configuration. A circuit-synthesis case study shows how our compiler exposes optimization tradeoffs.
ER -