Digital Etching of Single-Crystalline Silicon Fin Barriers Down to Sub-10 nm
Abstract
This work presents a fabrication process to realize sub-10 nm-thick, high-aspect-ratio Si fins using high-resistivity float-zone single-crystal Si wafers. Following anisotropic wet etching, a digital etching process based on repeated rapid thermal annealing (RTA) oxidation and vapor-phase hydrofluoric acid (VHF) etching of the resulting oxide was developed, enabling thinning of Si fins into the sub-10 nm regime. Cross-sectional scanning transmission electron microscopy confirms fin thicknesses as thin as 6 nm, although with a tapered profile resulting from the initial anisotropic wet etch. Tapering of the fin was reduced by using an N{_2}/O{_2} (5:1) ambient together with a reduced ramp rate during the temperature ramping for the RTA oxidation process. A thickness variation of 3 nm along a 1.2 μm tall fin was achieved on a fin with 12 nm near the top and 15 nm near the base. The developed process provides a pathway for fabricating Josephson junctions, setting a foundation toward reproducible and scalable superconducting qubit fabrication with single-crystal Si dielectric barriers using readily available Si processing technology.
Related
- Single-step initialization of a 16-channel silicon nitride DWDM demultiplexer using a physics-informed digital twin
- Hybrid Laser–Etching Fabrication of High-Density Antireflective Microstructures on DLC-Coated Silicon Using Burst-Mode Bessel Beam Processing
- From Simulation to Fabrication: Realizing Silicon Crystalline Undulators with Silicon Nitride Stressor Layer Patterning
- Non-contact temperature sensing and optical scatter in cryogenically-cooled crystalline silicon
- Josephson energy of superconducting junctions: amorphous versus crystalline tunnel barriers
BibTeX
@misc{wu2026digital,
title = {{Digital Etching of Single-Crystalline Silicon Fin Barriers Down to Sub-10 nm}},
author = {Yu Wu and Teun A. J. van Schijndel and Anthony P. McFadden and Wilson J. Yánez-Parreño and Raymond W. Simmonds and Christopher J. Palmstrøm},
howpublished = {arXiv},
year = {2026},
month = sep,
doi = {10.48550/arxiv.2609.32826},
eprint = {2609.32826},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2609.32826},
note = {CC BY 4.0},
}
RIS
TY - UNPB
TI - Digital Etching of Single-Crystalline Silicon Fin Barriers Down to Sub-10 nm
AU - Yu Wu
AU - Teun A. J. van Schijndel
AU - Anthony P. McFadden
AU - Wilson J. Yánez-Parreño
AU - Raymond W. Simmonds
AU - Christopher J. Palmstrøm
PY - 2026
DA - 2026/09/26
PB - arXiv
DO - 10.48550/arxiv.2609.32826
UR - https://arxiv.org/abs/2609.32826
AB - This work presents a fabrication process to realize sub-10 nm-thick, high-aspect-ratio Si fins using high-resistivity float-zone single-crystal Si wafers. Following anisotropic wet etching, a digital etching process based on repeated rapid thermal annealing (RTA) oxidation and vapor-phase hydrofluoric acid (VHF) etching of the resulting oxide was developed, enabling thinning of Si fins into the sub-10 nm regime. Cross-sectional scanning transmission electron microscopy confirms fin thicknesses as thin as 6 nm, although with a tapered profile resulting from the initial anisotropic wet etch. Tapering of the fin was reduced by using an N{_2}/O{_2} (5:1) ambient together with a reduced ramp rate during the temperature ramping for the RTA oxidation process. A thickness variation of 3 nm along a 1.2 μm tall fin was achieved on a fin with 12 nm near the top and 15 nm near the base. The developed process provides a pathway for fabricating Josephson junctions, setting a foundation toward reproducible and scalable superconducting qubit fabrication with single-crystal Si dielectric barriers using readily available Si processing technology.
ER -