Wafer-scale 2D MoS₂ transistors with sub-5 nm channel length and subthreshold performance beyond the silicon limit.
15 affiliations
- 1Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA.
- 2Mechanical Engineering, Carnegie Mellon University, Pittsburgh, PA, USA.
- 3Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA.
- 4Electrical Engineering and Computer Science, MIT, Cambridge, MA, USA.
- 5Materials Science and Engineering, Texas A&M University, College Station, TX, USA.
- 6Electrical and Computer Engineering, University of Southern California, Los Angeles, CA, USA.
- 7Information Processing and Telecommunications Center, Universidad Politécnica de Madrid, Madrid, Spain.
- 8Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA.
- 9Information Processing and Telecommunications Center, Universidad Politécnica de Madrid, Madrid, Spain. [email protected].
- 10Electrical Engineering and Computer Science, MIT, Cambridge, MA, USA. [email protected].
- 11Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA. [email protected].
- 12Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA. [email protected].
- 13Mechanical Engineering, Carnegie Mellon University, Pittsburgh, PA, USA. [email protected].
- 14Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA. [email protected].
- 15Mechanical Engineering, Carnegie Mellon University, Pittsburgh, PA, USA. [email protected].
Abstract
The downscaling of silicon field-effect transistors is approaching fundamental limits, with the international roadmap for devices and systems (IRDS) projecting a 12 nm channel length plateau by 2037. Two-dimensional (2D) semiconductors have emerged as promising candidates for extended transistor scaling. However, no experimental demonstration has thus far surpassed the fundamental switching limits of advanced silicon. Here, we report monolayer MoS₂ transistors with physical channel lengths below 5 nm, achieving a subthreshold swing of 88 mV/dec and an on/off ratio above 10⁶. These results surpass both the theoretical subthreshold limit of silicon and state-of-the-art emerging semiconductors-based transistors at comparable dimensions. To ensure high throughput, we develop a photolithography based, complementary metal oxide semiconductor (CMOS) compatible process and demonstrate 4-inch wafer-scale integration. We implement a design-technology co-optimization approach featuring an air-gap isolation and gate-contact overlap design to effectively suppress short channel effects. This work demonstrates subthreshold transport in a 2D semiconductor transistor beyond the silicon limit, showing a viable pathway for extending transistor scaling and energy-efficient computing.
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BibTeX
@article{lin2026waferscale,
title = {{Wafer-scale 2D MoS₂ transistors with sub-5 nm channel length and subthreshold performance beyond the silicon limit.}},
author = {S Lin and T Huang and N Yang and X Zheng and H Yang and H S Yun and G Turner and Y Zhong and J Zou and K Zhang and J Wu and J Grajal and Y C Lin and K Y Xie and H Wang and J Kong and J Guo and S Shen and X Zhang},
journal = {Nature communications},
year = {2026},
month = sep,
doi = {10.1038/s41467-026-77186-9},
url = {https://europepmc.org/article/MED/42907455},
note = {CC BY-NC-ND},
}
RIS
TY - JOUR
TI - Wafer-scale 2D MoS₂ transistors with sub-5 nm channel length and subthreshold performance beyond the silicon limit.
AU - S Lin
AU - T Huang
AU - N Yang
AU - X Zheng
AU - H Yang
AU - H S Yun
AU - G Turner
AU - Y Zhong
AU - J Zou
AU - K Zhang
AU - J Wu
AU - J Grajal
AU - Y C Lin
AU - K Y Xie
AU - H Wang
AU - J Kong
AU - J Guo
AU - S Shen
AU - X Zhang
PY - 2026
DA - 2026/09/21
JO - Nature communications
DO - 10.1038/s41467-026-77186-9
UR - https://europepmc.org/article/MED/42907455
AB - The downscaling of silicon field-effect transistors is approaching fundamental limits, with the international roadmap for devices and systems (IRDS) projecting a 12 nm channel length plateau by 2037. Two-dimensional (2D) semiconductors have emerged as promising candidates for extended transistor scaling. However, no experimental demonstration has thus far surpassed the fundamental switching limits of advanced silicon. Here, we report monolayer MoS₂ transistors with physical channel lengths below 5 nm, achieving a subthreshold swing of 88 mV/dec and an on/off ratio above 10⁶. These results surpass both the theoretical subthreshold limit of silicon and state-of-the-art emerging semiconductors-based transistors at comparable dimensions. To ensure high throughput, we develop a photolithography based, complementary metal oxide semiconductor (CMOS) compatible process and demonstrate 4-inch wafer-scale integration. We implement a design-technology co-optimization approach featuring an air-gap isolation and gate-contact overlap design to effectively suppress short channel effects. This work demonstrates subthreshold transport in a 2D semiconductor transistor beyond the silicon limit, showing a viable pathway for extending transistor scaling and energy-efficient computing.
SN - 2041-1723
ER -