Designer Codes from GALA: Compact, Self-Dual, and Rate-1/2 QEC on Reconfigurable Atom Arrays
Abstract
Achieving useful fault-tolerant applications requires co-designing the quantum error-correcting code for footprint, logical instruction set, and hardware compatibility simultaneously. Recent breakthroughs in ultra-high-rate codes have the potential to reduce footprint of large scale quantum applications but their practical utility is limited without an addressable logical instruction set and efficient implementation on near term hardware. Reconfigurable neutral atom arrays, for example, support only hundreds of qubits with constrained reconfigurability from a few crossed acousto-optic deflectors (AOD). We introduce the GALA codes, or Group-Action Lifts with Active orthogonality, that allows such co-design by construction. GALA lifts over a product group G = Hk × Cm (or Hk ltimes Cmk); the small non-abelian factor Hk supplies active orthogonality that improves qubit overhead, reaching 1/2 encoding rate with above-weight distance, while the large abelian factor Cm supplies symmetries that give code automorphisms and explicit, simple AOD move schedules. Logical addressibility and hardware compatibility follow directly from construction, rather than verified post-hoc. The GALA family contains several known rate-1/2 Kasai codes of Ref.[arXiv:2601.08824, arXiv:2604.16209] while exposing simpler parameter bounds, logical operations, and ZX-dual variants with AOD-compatible fold-transversal Clifford gates. In particular, we find a compact self-dual $[[132,30,12]]$ with 1.0+0.9−0.6× 10−9 per-round per-qubit logical error rate at 10−3 physical error rate, equipped with 3.1 ms syndrome-extraction cycles and an addressable logical instruction set; a ZX-dual, girth-6, rate-1/2 $[[672,336,12]]$ with a 6.76 ms cycles; and barrier-breaking $[[1752,880,14]]$ and $[[2232,1120,16]]$ smaller than previously known hardware-compatible rate-1/2 codes.
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BibTeX
@misc{yang2026designer,
title = {{Designer Codes from GALA: Compact, Self-Dual, and Rate-1/2 QEC on Reconfigurable Atom Arrays}},
author = {Willers Yang and Casey Duckering and Arpit Dua},
howpublished = {arXiv},
year = {2026},
month = oct,
doi = {10.48550/arxiv.2608.07431},
eprint = {2608.07431},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2608.07431},
}
RIS
TY - UNPB
TI - Designer Codes from GALA: Compact, Self-Dual, and Rate-1/2 QEC on Reconfigurable Atom Arrays
AU - Willers Yang
AU - Casey Duckering
AU - Arpit Dua
PY - 2026
DA - 2026/10/05
PB - arXiv
DO - 10.48550/arxiv.2608.07431
UR - https://arxiv.org/abs/2608.07431
AB - Achieving useful fault-tolerant applications requires co-designing the quantum error-correcting code for footprint, logical instruction set, and hardware compatibility simultaneously. Recent breakthroughs in ultra-high-rate codes have the potential to reduce footprint of large scale quantum applications but their practical utility is limited without an addressable logical instruction set and efficient implementation on near term hardware. Reconfigurable neutral atom arrays, for example, support only hundreds of qubits with constrained reconfigurability from a few crossed acousto-optic deflectors (AOD). We introduce the GALA codes, or Group-Action Lifts with Active orthogonality, that allows such co-design by construction. GALA lifts over a product group G = H_k × C_m (or H_k ltimes C_m^k); the small non-abelian factor H_k supplies active orthogonality that improves qubit overhead, reaching 1/2 encoding rate with above-weight distance, while the large abelian factor C_m supplies symmetries that give code automorphisms and explicit, simple AOD move schedules. Logical addressibility and hardware compatibility follow directly from construction, rather than verified post-hoc. The GALA family contains several known rate-1/2 Kasai codes of Ref.[arXiv:2601.08824, arXiv:2604.16209] while exposing simpler parameter bounds, logical operations, and ZX-dual variants with AOD-compatible fold-transversal Clifford gates. In particular, we find a compact self-dual $[[132,30,12]]$ with 1.0^+0.9_−0.6× 10^−9 per-round per-qubit logical error rate at 10^−3 physical error rate, equipped with 3.1 ms syndrome-extraction cycles and an addressable logical instruction set; a ZX-dual, girth-6, rate-1/2 $[[672,336,12]]$ with a 6.76 ms cycles; and barrier-breaking $[[1752,880,14]]$ and $[[2232,1120,16]]$ smaller than previously known hardware-compatible rate-1/2 codes.
ER -