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PreprintarXiv licencearXiv

Challenges in the verification of MOSAIX ASIC for ALICE ITS3

Abstract

The MOSAIX is a wafer-scale, full-functionality prototype ASIC for the ALICE Inner Tracking System (ITS3) upgrade, implemented in 65 nm stitching technology. It integrates 144 independently powered pixel matrices, eight 10 Gb/s serializers, and on-chip data and power distribution, making full-chip verification highly resource-intensive (over 80 GB of memory and 192,000 tests). Verification also targets a sophisticated power-up sequence and radiation conditions of 106\ particles s−1 cm−2 and 4 kGy TID. This work presents a UVM-based verification strategy that identified 260 design errors and summarizes key lessons from ASIC sign-off.

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BibTeX
@misc{scarfi2026challenges,
  title = {{Challenges in the verification of MOSAIX ASIC for ALICE ITS3}},
  author = {Simone Scarfi and Matteo Lupi and Adithya Pulli},
  howpublished = {arXiv},
  year = {2026},
  month = oct,
  doi = {10.48550/arxiv.2610.41916},
  eprint = {2610.41916},
  archivePrefix = {arXiv},
  url = {https://arxiv.org/abs/2610.41916},
}
RIS
TY  - UNPB
TI  - Challenges in the verification of MOSAIX ASIC for ALICE ITS3
AU  - Simone Scarfi
AU  - Matteo Lupi
AU  - Adithya Pulli
PY  - 2026
DA  - 2026/10/30
PB  - arXiv
DO  - 10.48550/arxiv.2610.41916
UR  - https://arxiv.org/abs/2610.41916
AB  - The MOSAIX is a wafer-scale, full-functionality prototype ASIC for the ALICE Inner Tracking System (ITS3) upgrade, implemented in 65 nm stitching technology. It integrates 144 independently powered pixel matrices, eight 10 Gb/s serializers, and on-chip data and power distribution, making full-chip verification highly resource-intensive (over 80 GB of memory and 192,000 tests). Verification also targets a sophisticated power-up sequence and radiation conditions of 10^6\ particles s^−1 cm^−2 and 4 kGy TID. This work presents a UVM-based verification strategy that identified 260 design errors and summarizes key lessons from ASIC sign-off.
ER  -