A flexible DAQ system for the Timepix4 ASIC in the 4DPHOTON project
Abstract
This paper presents the design and implementation of a flexible data acquisition system13 developed for the Timepix4 ASIC. The system is based on a modular14 FPGA-centric architecture combining high-speed serial readout, Ethernet-based data transport,15 and deterministic multi-board synchronization. The hardware platform includes a scalable stack16 composed of commercial FPGA carrier boards, FMC-based interface electronics, detector-specific17 chipboards, and a dedicated Trigger Logic Unit for synchronized operation.18 The firmware architecture separates control and data paths, enabling independent configuration19 and high-throughput acquisition through UDP over 10 GbE links. The design supports zero-back-20 pressure operation toward the ASIC and allows adaptation of the readout bandwidth to different21 experimental conditions. Synchronization between multiple DAQ systems is achieved through22 a common clock and trigger distribution network, experimentally demonstrated with sub-100 ps23 precision.24 The system has been developed to support detector characterization, laboratory measurements,25 and beam-test campaigns for the 4DPHOTON detector concept. Hardware organization, firmware26 architecture, synchronization strategy, and performance measurements are presented.
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BibTeX
@misc{biesuz2026flexible,
title = {{A flexible DAQ system for the Timepix4 ASIC in the 4DPHOTON project}},
author = {N. V. Biesuz and J. Alozy and R. Bolzonella and V. Cavallini and A. Cotta Ramusino and M. Fiorini and E. Franzoso and X. Llopart Cudie and A. Saputi},
howpublished = {arXiv},
year = {2026},
month = sep,
doi = {10.48550/arxiv.2607.14847},
eprint = {2607.14847},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2607.14847},
note = {CC BY-SA 4.0},
}
RIS
TY - UNPB
TI - A flexible DAQ system for the Timepix4 ASIC in the 4DPHOTON project
AU - N. V. Biesuz
AU - J. Alozy
AU - R. Bolzonella
AU - V. Cavallini
AU - A. Cotta Ramusino
AU - M. Fiorini
AU - E. Franzoso
AU - X. Llopart Cudie
AU - A. Saputi
PY - 2026
DA - 2026/09/11
PB - arXiv
DO - 10.48550/arxiv.2607.14847
UR - https://arxiv.org/abs/2607.14847
AB - This paper presents the design and implementation of a flexible data acquisition system13 developed for the Timepix4 ASIC. The system is based on a modular14 FPGA-centric architecture combining high-speed serial readout, Ethernet-based data transport,15 and deterministic multi-board synchronization. The hardware platform includes a scalable stack16 composed of commercial FPGA carrier boards, FMC-based interface electronics, detector-specific17 chipboards, and a dedicated Trigger Logic Unit for synchronized operation.18 The firmware architecture separates control and data paths, enabling independent configuration19 and high-throughput acquisition through UDP over 10 GbE links. The design supports zero-back-20 pressure operation toward the ASIC and allows adaptation of the readout bandwidth to different21 experimental conditions. Synchronization between multiple DAQ systems is achieved through22 a common clock and trigger distribution network, experimentally demonstrated with sub-100 ps23 precision.24 The system has been developed to support detector characterization, laboratory measurements,25 and beam-test campaigns for the 4DPHOTON detector concept. Hardware organization, firmware26 architecture, synchronization strategy, and performance measurements are presented.
ER -