Void-Free Through-Glass Vias for Multilayer Surface-Electrode Ion Traps
Abstract
Through-substrate interconnects are a key technology for scaling surface-electrode ion traps (SEITs) toward large electrode counts and complex architectures. Dielectric substrates such as fused silica offer superior RF performance compared to silicon, but the reliable fabrication of void-free through-glass vias (TGVs) remains challenging. In this work, we demonstrate a SEIT fabricated on a fused silica substrate incorporating TGVs. The via-holes are formed using Selective Laser-Induced Etching and subsequently metallized with gold by electroplating. A patent-pending geometry-assisted bottom-up plating approach enables void-free filling using constant-current electroplating without electrolyte additives or pulsed deposition schemes. Electrical characterization across multiple wafers confirms a TGV-level yield above 98.8 %, demonstrating the robustness and reproducibility of the developed TGV technology. The TGVs are combined with multilayer SEIT fabrication, enabling vertical signal routing to all electrodes while maintaining an unaffected trapping surface without wire bonds. To interface the trap with external control electronics, a glass interposer providing signal fan-out to a larger pitch is designed and fabricated. The trap chip and the interposer are integrated using thermocompression bonding, forming a compact chip-to-chip assembly. The presented technology demonstrates the first fully integrated multilayer SEIT on fused silica incorporating void-free TGVs.
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BibTeX
@misc{iseke2026voidfree,
title = {{Void-Free Through-Glass Vias for Multilayer Surface-Electrode Ion Traps}},
author = {Eike Iseke and Jacob Stupp and Friederike Giebel and Nila Krishnakumar and Konstantin Thronberens and Nora D. Stahr and Md. Masum Billah and Marlon Kuhn and Christian Ospelkaus},
howpublished = {arXiv},
year = {2026},
month = oct,
doi = {10.48550/arxiv.2610.19736},
eprint = {2610.19736},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2610.19736},
}
RIS
TY - UNPB
TI - Void-Free Through-Glass Vias for Multilayer Surface-Electrode Ion Traps
AU - Eike Iseke
AU - Jacob Stupp
AU - Friederike Giebel
AU - Nila Krishnakumar
AU - Konstantin Thronberens
AU - Nora D. Stahr
AU - Md. Masum Billah
AU - Marlon Kuhn
AU - Christian Ospelkaus
PY - 2026
DA - 2026/10/14
PB - arXiv
DO - 10.48550/arxiv.2610.19736
UR - https://arxiv.org/abs/2610.19736
AB - Through-substrate interconnects are a key technology for scaling surface-electrode ion traps (SEITs) toward large electrode counts and complex architectures. Dielectric substrates such as fused silica offer superior RF performance compared to silicon, but the reliable fabrication of void-free through-glass vias (TGVs) remains challenging. In this work, we demonstrate a SEIT fabricated on a fused silica substrate incorporating TGVs. The via-holes are formed using Selective Laser-Induced Etching and subsequently metallized with gold by electroplating. A patent-pending geometry-assisted bottom-up plating approach enables void-free filling using constant-current electroplating without electrolyte additives or pulsed deposition schemes. Electrical characterization across multiple wafers confirms a TGV-level yield above 98.8 %, demonstrating the robustness and reproducibility of the developed TGV technology. The TGVs are combined with multilayer SEIT fabrication, enabling vertical signal routing to all electrodes while maintaining an unaffected trapping surface without wire bonds. To interface the trap with external control electronics, a glass interposer providing signal fan-out to a larger pitch is designed and fabricated. The trap chip and the interposer are integrated using thermocompression bonding, forming a compact chip-to-chip assembly. The presented technology demonstrates the first fully integrated multilayer SEIT on fused silica incorporating void-free TGVs.
ER -