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PreprintCC BY 4.0arXiv

Design and Modeling of the Charge Readout of a SiMOS Quantum Dot with a Single Electron Transistor and CryoCMOS

  • Adam Quinn
  • Troy England
  • Andrew Li
  • Sharmila Mustari Nandita
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Abstract

Single electron spin qubits trapped in SiMOS quantum dots are a promising technology for scaling to thousand- or million-qubit systems due to their compatibility with mature CMOS manufacturing processes. A readout system that combines a single electron transistor with a custom cryogenic CMOS amplification and digitization chain offers key advantages by avoiding the use of bulky RF components or room-temperature interconnects. We present design techniques and simulation results for an optimized qubit-SET cryoCMOS interface, culminating in the design of the QNDR1 ASIC, the first cryogenic readout ASIC designed under the Quandarum project, which targets the development of a many-channel spin qubit based detector for use in high energy physics.

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Cite

BibTeXRIS
BibTeX
@misc{quinn2026design,
  title = {{Design and Modeling of the Charge Readout of a SiMOS Quantum Dot with a Single Electron Transistor and CryoCMOS}},
  author = {Adam Quinn and Troy England and Andrew Li and Sharmila Mustari Nandita},
  howpublished = {arXiv},
  year = {2026},
  month = aug,
  doi = {10.48550/arxiv.2608.28906},
  eprint = {2608.28906},
  archivePrefix = {arXiv},
  url = {https://arxiv.org/abs/2608.28906},
  note = {CC BY 4.0},
}
RIS
TY  - UNPB
TI  - Design and Modeling of the Charge Readout of a SiMOS Quantum Dot with a Single Electron Transistor and CryoCMOS
AU  - Adam Quinn
AU  - Troy England
AU  - Andrew Li
AU  - Sharmila Mustari Nandita
PY  - 2026
DA  - 2026/08/28
PB  - arXiv
DO  - 10.48550/arxiv.2608.28906
UR  - https://arxiv.org/abs/2608.28906
AB  - Single electron spin qubits trapped in SiMOS quantum dots are a promising technology for scaling to thousand- or million-qubit systems due to their compatibility with mature CMOS manufacturing processes. A readout system that combines a single electron transistor with a custom cryogenic CMOS amplification and digitization chain offers key advantages by avoiding the use of bulky RF components or room-temperature interconnects. We present design techniques and simulation results for an optimized qubit-SET cryoCMOS interface, culminating in the design of the QNDR1 ASIC, the first cryogenic readout ASIC designed under the Quandarum project, which targets the development of a many-channel spin qubit based detector for use in high energy physics.
ER  -