Real-Time SiPM Pulse Deconvolution for a High-granularity Dual-readout Calorimeter with Neutral Networks
Abstract
The High-Granularity Dual-Readout Calorimeter (HG-DREAM) designed for FCC-ee aims to achieve unprecedented energy resolution through fine three-dimensional shower imaging, simultaneous measurement of Cherenkov and scintillation signals, and machine learning capabilities. A key enabling technology is longitudinal segmentation via timing measurements, where multiple energy deposits along optical fibers are distinguished by the arrival times of Cherenkov photons. We present quantized one-dimensional convolutional neural networks that predict pulse locations directly from 80-sample, 16 ns waveforms digitized at 200 ps, and evaluate their implementation in front-end electronics. Three architectures, a compact baseline and two variants using dilation and stride to reach the ∼ 20-sample receptive field set by the SiPM pulse width, achieve ROC AUC above 0.95 with four to eight filters per layer. Fixed-point quantization to a <16,8> baseline costs less than 10−3 in AUC relative to the floating-point reference. Applied to pairwise deposits, the smallest model separates two pulses with better than 95\% probability at longitudinal separations of 20 cm and above. Synthesized at 400 MHz, this model uses 9663 LUT on a Xilinx XCVU13P FPGA and occupies ∼ 18500 μm2 in TSMC 28 nm CMOS with reconfigurable weights. Assuming a triggered readout architecture for FCC-ee, the ∼ 500 kHz Z-pole trigger rate will be the most stringent throughput requirement across all FCC-ee operating modes. The ASIC implementation of the model sustains 4.8 MHz, exceeding the 0.5 MHz requirement by an order of magnitude, while the reconfigurable-weight FPGA implementation fails to do so. Sustaining the 40 MHz FCC-ee Z-pole bunch-crossing frequency in the triggerless architecture is not feasible with the models developed and the hardware targeted in this work.
Related
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BibTeX
@misc{allen2026realtime,
title = {{Real-Time SiPM Pulse Deconvolution for a High-granularity Dual-readout Calorimeter with Neutral Networks}},
author = {Spencer Allen and Matteo Cremonesi and Jordan Damgov and Erdem Yigit Ertorer and Janna Goodman and Giuseppe Di Guglielmo and James Hirschauer and Shuichi Kunori and Peter Meiring},
howpublished = {arXiv},
year = {2026},
month = sep,
doi = {10.48550/arxiv.2609.22269},
eprint = {2609.22269},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2609.22269},
}
RIS
TY - UNPB
TI - Real-Time SiPM Pulse Deconvolution for a High-granularity Dual-readout Calorimeter with Neutral Networks
AU - Spencer Allen
AU - Matteo Cremonesi
AU - Jordan Damgov
AU - Erdem Yigit Ertorer
AU - Janna Goodman
AU - Giuseppe Di Guglielmo
AU - James Hirschauer
AU - Shuichi Kunori
AU - Peter Meiring
PY - 2026
DA - 2026/09/09
PB - arXiv
DO - 10.48550/arxiv.2609.22269
UR - https://arxiv.org/abs/2609.22269
AB - The High-Granularity Dual-Readout Calorimeter (HG-DREAM) designed for FCC-ee aims to achieve unprecedented energy resolution through fine three-dimensional shower imaging, simultaneous measurement of Cherenkov and scintillation signals, and machine learning capabilities. A key enabling technology is longitudinal segmentation via timing measurements, where multiple energy deposits along optical fibers are distinguished by the arrival times of Cherenkov photons. We present quantized one-dimensional convolutional neural networks that predict pulse locations directly from 80-sample, 16 ns waveforms digitized at 200 ps, and evaluate their implementation in front-end electronics. Three architectures, a compact baseline and two variants using dilation and stride to reach the ∼ 20-sample receptive field set by the SiPM pulse width, achieve ROC AUC above 0.95 with four to eight filters per layer. Fixed-point quantization to a <16,8> baseline costs less than 10^−3 in AUC relative to the floating-point reference. Applied to pairwise deposits, the smallest model separates two pulses with better than 95\% probability at longitudinal separations of 20 cm and above. Synthesized at 400 MHz, this model uses 9663 LUT on a Xilinx XCVU13P FPGA and occupies ∼ 18500 μm^2 in TSMC 28 nm CMOS with reconfigurable weights. Assuming a triggered readout architecture for FCC-ee, the ∼ 500 kHz Z-pole trigger rate will be the most stringent throughput requirement across all FCC-ee operating modes. The ASIC implementation of the model sustains 4.8 MHz, exceeding the 0.5 MHz requirement by an order of magnitude, while the reconfigurable-weight FPGA implementation fails to do so. Sustaining the 40 MHz FCC-ee Z-pole bunch-crossing frequency in the triggerless architecture is not feasible with the models developed and the hardware targeted in this work.
ER -