First Demonstration of Flip DRAM from Process, Architecture to System to Push DRAM Scaling beyond 4F2: 2F2 Self-aligned Flip Vertical Channel Transistor (FVCT) DRAM and Flip WL (FWL) 3D-DRAM
Abstract
For the first time, we proposed a novel stacking technology for DRAM scaling by flipping and backside processes, making full use of DRAM wafer's backside and investigating it on both 4F2 and 3D-DRAM. For 4F2 VCT, 2F2 Flip VCT featuring self-aligned back-to-back stacked 1T1C bitcell, with various BL and WL configurations, were studied and key process modules such as self-aligned stacked vertical channel, BL and WL formations, wafer bonding and flipping, substrate thinning and low-R Co storage node (SN) were successfully developed, addressing the potential thermal, misalign and parasitic concerns in the Flip VCT process. A full DRAM DTCO framework was also established from device to mat and chip level. Compared to 4F2 VCT DRAM with the same mat size, 2F2 FVCT delivers 27.5% less parasitics, 11% better sense margin, 16.3% higher charge sharing (CS) speed and 50% less area. For 3D-DRAM, a brand-new flip WL staircase design with peripheral circuit innovations was studied and proved to have 25% density gain, 15.1% faster turn-on speed and 6.8% less CS time, proving further extendibility of flip technology on DRAM.
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BibTeX
@misc{liu2026first,
title = {{First Demonstration of Flip DRAM from Process, Architecture to System to Push DRAM Scaling beyond 4F2: 2F2 Self-aligned Flip Vertical Channel Transistor (FVCT) DRAM and Flip WL (FWL) 3D-DRAM}},
author = {Yu Liu and Xinyue He and Yanbang Chu and Siyuan Liu and Jianxiang Jin and Fangcheng Sun and Yuyang Qiao and Xu Tian and Lan Li and Baokang Peng and Lining Zhang and Xing Wu and Pengpeng Ren and Zhigang Ji and Zongwei Wang and Lijie Zhang and Xinwei Wan and Weihai Bu and Ming Li and Runsheng Wang and Heng Wu and Ru Huang},
howpublished = {arXiv},
year = {2026},
month = sep,
doi = {10.48550/arxiv.2609.14464},
eprint = {2609.14464},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2609.14464},
}
RIS
TY - UNPB
TI - First Demonstration of Flip DRAM from Process, Architecture to System to Push DRAM Scaling beyond 4F2: 2F2 Self-aligned Flip Vertical Channel Transistor (FVCT) DRAM and Flip WL (FWL) 3D-DRAM
AU - Yu Liu
AU - Xinyue He
AU - Yanbang Chu
AU - Siyuan Liu
AU - Jianxiang Jin
AU - Fangcheng Sun
AU - Yuyang Qiao
AU - Xu Tian
AU - Lan Li
AU - Baokang Peng
AU - Lining Zhang
AU - Xing Wu
AU - Pengpeng Ren
AU - Zhigang Ji
AU - Zongwei Wang
AU - Lijie Zhang
AU - Xinwei Wan
AU - Weihai Bu
AU - Ming Li
AU - Runsheng Wang
AU - Heng Wu
AU - Ru Huang
PY - 2026
DA - 2026/09/13
PB - arXiv
DO - 10.48550/arxiv.2609.14464
UR - https://arxiv.org/abs/2609.14464
AB - For the first time, we proposed a novel stacking technology for DRAM scaling by flipping and backside processes, making full use of DRAM wafer's backside and investigating it on both 4F2 and 3D-DRAM. For 4F2 VCT, 2F2 Flip VCT featuring self-aligned back-to-back stacked 1T1C bitcell, with various BL and WL configurations, were studied and key process modules such as self-aligned stacked vertical channel, BL and WL formations, wafer bonding and flipping, substrate thinning and low-R Co storage node (SN) were successfully developed, addressing the potential thermal, misalign and parasitic concerns in the Flip VCT process. A full DRAM DTCO framework was also established from device to mat and chip level. Compared to 4F2 VCT DRAM with the same mat size, 2F2 FVCT delivers 27.5% less parasitics, 11% better sense margin, 16.3% higher charge sharing (CS) speed and 50% less area. For 3D-DRAM, a brand-new flip WL staircase design with peripheral circuit innovations was studied and proved to have 25% density gain, 15.1% faster turn-on speed and 6.8% less CS time, proving further extendibility of flip technology on DRAM.
ER -